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MyHDL〔http://www.myhdl.org〕 is a Python based hardware description language (HDL). Features of MyHDL include: * The ability to generate VHDL and Verilog code from a MyHDL design.〔http://www.myhdl.org/doc/current/manual/conversion.html〕 * The ability to generate a testbench (Conversion of test benches〔http://www.myhdl.org/doc/current/whatsnew/0.6.html#conversion-of-test-benches〕) with test vectors in VHDL or Verilog, based on complex computations in Python. * The ability to convert a lists of signals.〔http://www.myhdl.org/doc/current/whatsnew/0.6.html#conversion-of-lists-of-signals〕 * The ability to convert output verification.〔http://www.myhdl.org/doc/current/whatsnew/0.6.html#conversion-output-verification〕 * The ability to do Co-simulation with Verilog.〔http://www.myhdl.org/doc/current/manual/cosimulation.html〕 * An advanced datatype system, independent of traditional datatypes. MyHDL's translator tool automatically writes conversion functions when the target language requires them. MyHDL is developed by Jan Decaluwe.〔http://www.linuxjournal.com/article/7542〕 == Conversion Examples == Here, you can see some examples of conversions from MyHDL designs to VHDL and/or Verilog.〔http://www.myhdl.org/doc/current/manual/conversion_examples.html〕 A small combinatorial design The example is a small combinatorial design, more specifically the binary to Gray code converter: def bin2gray(B, G, width): """ Gray encoder. B -- input intbv signal, binary encoded G -- output intbv signal, gray encoded width -- bit width """ @always_comb def logic(): Bext = intbv(0)() Bext() = B for i in range(width): G.next() = Bext() ^ Bext() return logic You can create an instance and convert to Verilog and VHDL as follows: width = 8 B = Signal(intbv(0)()) G = Signal(intbv(0)()) bin2gray_inst = toVerilog(bin2gray, B, G, width) bin2gray_inst = toVHDL(bin2gray, B, G, width) The generated Verilog code looks as follows: module bin2gray ( B, G ); input () B; output () G; reg () G; always @(B) begin: BIN2GRAY_LOGIC integer i; reg () Bext; Bext = 9'h0; Bext = B; for (i=0; i<8; i=i+1) begin G() <= (Bext(+ 1) ) ^ Bext()); end end endmodule The generated VHDL code looks as follows: library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_06.all; entity bin2gray is port ( B: in unsigned(7 downto 0); G: out unsigned(7 downto 0) ); end entity bin2gray; architecture MyHDL of bin2gray is begin BIN2GRAY_LOGIC: process (B) is variable Bext: unsigned(8 downto 0); begin Bext := to_unsigned(0, 9); Bext := resize(B, 9); for i in 0 to 8-1 loop G(i) <= (Bext((i + 1)) xor Bext(i)); end loop; end process BIN2GRAY_LOGIC; end architecture MyHDL; 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「MyHDL」の詳細全文を読む スポンサード リンク
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